Page 62 - 2025 TSIA年刊

2025 黃柏崴 Bo-Wei Huang 得獎經歷 / 專利 • 2024 年電子所學生傑出研究獎 • 2024 年美光半導體創新應用競賽 (Mimory Award) 優秀獎 • 2022 年 MRS-T 華立創新材料大賽 (Wah Lee Material Innovation Award) 金質獎 • 2022~2023 年「1975 級電機系系友科技研究創新獎」 重要學術著作 • 2021 年「Dialog 戴樂格半導體獎勵學生優良研究成果獎」 • 2021 年台積電博士獎學金 • 2021 年臺大學士班論文院長獎 • 申請中發明專利:美國 6 件 (3 項第一發明人，3 項共同發明人 ) 國立臺灣大學 電子工程學研究所 獲獎摘要 黃柏崴同學於 2021 年學士逕讀國立臺灣大學電子工程學研究所博士班，研究領域為高載子遷 移率奈米片電晶體、互補式場校電晶體 (CFET) 與電晶體堆疊，利用改善電晶體結構，進一步 提升電晶體密度。相關研究成果發表於 IEEE 頂尖國際會議 Symposium on VLSI Technology、 International Electron Devices Meeting 和 IEEE EDL、IEEE TED 等國際期刊。參與發表 14 篇國 際期刊 (2 篇第一作者 )、9 篇 IEDM 及 VLSI 國際研討會論文 (2 篇第一作者 ) 以及 12 篇其他研討 會論文 (3 篇第一作者 )。 1. Bo-Wei Huang, Ying-Qi Liu, Ching-Wang Yao, Wei-Jen Chen, Min Kuan Lin, Xin-Yuan Lin, Chun-Yi Cheng, Yi Huang, Ding-Wei Lin, Chih-Hsuan Lu, Tsung-Han Tsai, and C. W. Liu, "First Demonstration of Monolithic 3-Tier Nanosheet Transistor Stacking with Split Gate Featuring Tri-State Inverter/Half SRAM Functionalities," Symposium on VLSI Technology and Circuits (VLSI), JUNE 8-12, 2025. 2. Bo-Wei Huang, Chun-Yi Cheng, Wan-Hsuan Hsieh, Yu-Rui Chen, Wei-Jen Chen, Yi-Chun Liu, Min-Kuan Lin, Ying-Qi Liu, Hao-Yi Lu, Yi Huang, Ding-Wei Lin, and C. W. Liu, "WNxCy VT Tuning of Split Gate Nanosheet CFET with Dual Work Function Metals Achieving 0.93 VT Match/ Improved 0.24V Noise Margin/ Record Gain of 61V/V," 2024 IEEE International Electron Devices Meeting(IEDM), San Francisco, CA, USA, Dec. 2024. 3. Bo-Wei Huang, Wan-Hsuan Hsieh, Chien-Te Tu, Yi-Chun Liu, Yu-Rui Chen, Wei-Jen Chen, Chun-Yi Cheng, Hung-Chun Chou, and C. W. Liu, "Breakdown Voltage Enhancement of Nanosheet Transistors by Ultrathin Bodies," IEEE Electron Device Letters, vol. 45, no. 6, pp.956-959, June 2024. 4. Bo-Wei Huang, Chung-En Tsai, Yi-Chun Liu, Chien-Te Tu, Wan-Hsuan Hsieh, Sun-Rong Jan, Yu-Rui Chen, Shee-Jier Chueh, Chun-Yi Cheng, and C. W. Liu, "Highly Stacked GeSn Nanosheets by CVD Epitaxy and Highly Selective Isotropic Dry Etching," IEEE Transactions on Electron Devices, Vol. 69, No. 4, pp. 2130-2136, Apr. 2022. 5. Chung-En Tsai, Yi-Chun Liu, Chien-Te Tu, Bo-Wei Huang, Sun-Rong Jan, Yu-Rui Chen, Jyun-Yan Chen, Shee-Jier Chueh, Chun-Yi Cheng, Chia-Jung Tsen, Yichen Ma, and C. W. Liu, "Highly Stacked 8 Ge0.9Sn0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record ION/IOFF of 1.4x107 and Record ION of 92μA at VOV=VDS= -0.5V by CVD Epitaxy and Dry Etching," pp. 569-572, International Electron Devices Meeting (IEDM), 2021. 6. Bo-Wei Huang, Wei-Jen Chen, Yu-Rui Chen, and C. W. Liu, "Enhanced Breakdown Voltage and Photo Response of Ultrathin Body Nanosheets," accepted by 55th IEEE Semiconductor Interface Specialists Conference (SISC), Dec. 11-14, 2024. 7. Bo-Wei Huang, Yu-Rui Chen, Tao Chou, Hsin-Cheng Lin, Chien-Te Tu, Yi-Chun Liu, Wan-Hsuan Hsieh, Wei-Jen Chen, Min-Kuan Lin, Ying-Qi Liu, Li- Kai Wang, Hung-Chun Chou, Yi Huang, Ding-Wei Lin, and C. W. Liu, "Enhanced Electrical Performance of Ultrathin Body Nanosheets," IEEE Silicon Nanoelectronics Workshop (SNW), Jun. 15 - 16, 2024. 8. Chien-Te Tu, Wan-Hsuan Hsieh, Yu-Rui Chen, Bo-Wei Huang, Yu-Tsung Liao, Wei-Jen Chen, Yi-Chun Liu, Chun-Yi Cheng, Hung-Chun Chou, Hao-Yi Lu, Cheng-Hsien Hsin, Geng-Min He, Dong Soo Woo, Shee-Jier Chueh, and C. W. Liu, "First Demonstration of Monolithic Self-aligned Heterogeneous Nanosheet Channel Complementary FETs with Matched VT by Band Alignments of Individual Channels," International Electron Devices Meeting (IEDM), Dec. 9-13, 2023. 9. Chien-Te Tu, Yi-Chun Liu, Bo-Wei Huang, Yu-Rui Chen, Wan-Hsuan Hsieh, Chung-En Tsai, Shee-Jier Chueh, Chun-Yi Cheng, Yichen Ma, and C. W. Liu, "First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation," pp. 479-482, International Electron Devices Meeting (IEDM), 2022. 10. Chia-Che Chung, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chia-Jung Tsen, and C. W. Liu, "Self-Heating of FinFET Circuitry Simulated by Multi- Correlated Recurrent Neural Networks," IEEE Electron Device Letters, vol. 43, no. 8, pp. 1179-1182, Aug. 2022. 60 指導教授 劉致為 特聘教授 現職 · Distinguished / Chair Professor, National Taiwan University 學歷 · Ph.D. 1994 Electrical Engineering, Princeton University · M.S. 1987 and B.S. 1985, National Taiwan University 經歷 · IEEE Fellow (2018~) · Deputy General Director (2008~2013) / Senior full researcher (2011~2019), National Nano Device Labs · Research Director / Senior full researcher; ERSO/ITRI (2002~2005) · CEO, tsmc-NTU research center (2013~2023)